Pat Gelsinger has backed Nagare Labs and its Z2RAM technology. The former Intel CEO is supporting an effort to combine SRAM-level bandwidth, DRAM-level density, and NAND-style manufacturing in one part. The move highlights ongoing pressure on system designers who must work around limits in how fast memory can supply data to processors and accelerators.
The memory wall problem
The memory wall describes the persistent gap between rapid gains in compute performance and slower improvements in memory access. Processors can execute instructions at rates that outstrip the ability of conventional memory to deliver operands and instructions. This mismatch forces architects to insert multiple cache levels, specialized interconnects, and sometimes entirely separate memory pools, each adding complexity and power draw.
Z2RAM is presented as a direct response to that constraint. The technology is described as matching SRAM bandwidth for fast random access, matching DRAM density for practical capacity per die, and using manufacturing flows comparable to NAND for cost and volume scaling. If realized, such a part would reduce reliance on layered cache hierarchies and allow simpler memory subsystems in servers, GPUs, and AI accelerators.
Prior attempts and current market state
The source reporting notes that the road for Nagare Labs is arduous and that similar claims have appeared from earlier memory startups. Those efforts largely ended without reaching sustained high-volume production or acceptable yields. The current market remains dominated by established DRAM and NAND suppliers whose processes have been refined across multiple technology nodes and whose supply chains support the bulk of global computing.
No public details exist on Nagare Labs’ funding size, valuation, development timeline, or manufacturing partners. The available account contains only the three performance targets and Gelsinger’s involvement. No competing memory approaches or rival startups are referenced in the source material.
Technical targets stated for Z2RAM
The pitch rests on three simultaneous attributes. Bandwidth is claimed to reach SRAM levels, which would support the high request rates typical of on-chip caches. Density is claimed to reach DRAM levels, which would allow larger working sets without proportional increases in die area. Manufacturing is claimed to follow NAND-style processes, which benefit from mature high-volume fabs and lower cost per bit than logic or SRAM processes.
These targets address different parts of the memory hierarchy at once. SRAM excels at speed but occupies too much area for large capacities. DRAM improves density yet requires periodic refresh and delivers lower bandwidth per pin. NAND achieves the lowest cost per bit yet operates too slowly for direct use as main memory. Combining the three in one device would require fundamental changes in cell design, interconnect, and process integration.
Why it matters
A part that actually delivered all three attributes would alter the constraints that shape processor and accelerator design. System architects could reduce cache area, simplify memory controllers, and allocate more silicon to compute or specialized units. Power and latency budgets would shift because fewer data-movement stages would sit between cores and main storage.
Yet the source itself flags the history of comparable promises that did not reach production. Memory technology has high barriers to entry: yield, reliability, and cost must all be proven at scale before customers commit designs. Until Nagare Labs produces working silicon that meets the stated targets in volume, the claims remain untested against those barriers. The decisive evidence will be measured in delivered wafers, not in pitch decks.
---
Sources:
[
{
"publisher": "The Register",
"title": "Former Intel CEO Pat Gelsinger bets on Nagare Labs to vault the memory wall",
"url": "https://www.theregister.com/systems/2026/10/26/former-intel-ceo-pat-gelsinger-bets-on-nagare-labs-to-vault-the-memory-wall/5305181",
"published_at": "2026-10-26T12:00:00.000Z",
"summary": "SRAM-like bandwidth, DRAM-like density, and NAND-like manufacturing: Z2RAM makes big promises, but the road ahead is arduous and littered with the ruins of failed memory vendors"
}
]
No comments yet